A voltage reference is a circuit that outputs a DC voltage signal. It can be employed on systems, sub-systems, and/or devices that need a voltage reference level for various purposes, such as to precisely generate DC voltages or digital clock signals. Voltage reference circuits are used in many electronic fields in many technologies, such as in NAND flash memory. FIGS. 1a and 1b depict block diagrams illustrating generic architectures of exemplary voltage reference circuits.
FIG. 1a depicts an analog circuit A having an output connected to a gate of a PMOS transistor M. The source and bulk terminals of the transistor M both connect to Vcc, which is the power supply of the system. The drain terminal of the transistor M connects to a resistor R. The output of the circuit, Vout, is given by Vout=R*Im, where Im is the current flowing through the transistor M. In this case, the load is the resistor R.
FIG. 1b depicts an analog circuit A having an output connected to a gate of a PMOS transistor M. As with FIG. 1a, the source and bulk terminals of the transistor M both connect to Vcc. The drain terminal of the transistor M connects to a cascade of MOS transistors M1, M2, and M3 in a diode configuration. The transistors in the cascade are depicted as NMOS transistors, though PMOS transistors may be used as well. In this case, the load is the chain of NMOS transistors.
The output of these circuits, Vout, can be used in various applications. For example, Vout can be used in a voltage regulator as a reference to generate higher or lower voltage levels, in an oscillator to generate digital clock signals with a precise period value, or in a comparator to define the comparator voltage threshold.
In some applications, it is necessary for the reference voltage Vout to be insensitive to temperature and power supply variations. For example, the above architectures can be applied in the case of a band-gap voltage generator, as illustrated in FIG. 2, and in the case of a current mirror, as illustrated in FIGS. 3 and 4.
FIG. 2 depicts a general schematic of an exemplary band-gap voltage generator. Compensation network N can be composed of bipolar junction transistors and resistors so that output node VREF is compensated over temperature. VIP connects to a positive input of an operational amplifier AMP while VIN connects to a negative input of AMP. The output node of AMP connects to the gate terminal of the M4 and M5 PMOS transistors. AMP can equalize the VIP and VIN nodes and stabilize the amplifier's operation using negative feedback. The source and bulk terminals of the M4 and M5 transistors connect to Vcc. The drain terminal of the M4 transistor connects to compensation network N and the drain terminal of the M5 transistor connects to the resistor ROUT. According to this configuration, the band-gap voltage generator can output a reference voltage VREF that is insensitive to both temperature and power supply variations.
FIG. 3 depicts a current mirror with a PMOS structure. A current mirror is a circuit configured to copy (i.e., mirror) a current passing through one active device by controlling the current in another active device while keeping the output current constant regardless of loading. In FIG. 3, IS is an ideal current source that generates a current I. The current I is mirrored by the M6 and M7 PMOS transistors. The output of the circuit VOUT is given by VOUT=R*I. As still another example, FIG. 4 depicts a variation of a current mirror in which the output voltage VOUT is referred to Vcc instead of ground.
In many of these applications, it is necessary to correct the value of the output voltage over the possible spreads and variations that may result from various factors. Some exemplary factors are resistivity variations for resistors, threshold voltage and trans-conductance variations for MOS transistors, and the like. An exemplary trimming technique and circuit therefor to correct the output voltage value is illustrated in FIG. 5.
FIG. 5 shows an analog circuit A having an output connected to a gate of a PMOS transistor M. The source and bulk terminals of the M transistor both connect to Vcc, where Vcc is the power supply of the system. The drain terminal of the M transistor connects to a resistor R1. Resistor R1 connects to ground through a chain of resistors—R2, R3, . . . , Rk−1, Rk, . . . , Rn. This creates a resistive partition from which multiple voltage levels may be extracted—V1, V2, V3, Vk−1, Vk, . . . , Vn. The voltages can be selectively extracted using a multiplexer, such as MUX1 shown in FIG. 5. The voltages that can be extracted can be represented as follows:V1=(R1+R2+R3+ . . . +Rk−1Rk+ . . . +Rn)*I, V2=(R2+R3+ . . . +Rk−1+Rk+ . . . +Rn)*I, V3=(R3+ . . . Rk−1+Rk+ . . . +Rn)*I, Vk−1=(Rk−1+Rk+ . . . +Rn)*I, Vk=(Rk+ . . . +Rn)*I, where I is the current flowing through transistor M.
Voltage extraction can be performed as follows. The various voltages can be connected to the inputs of multiplexer MUX1. MUX1 can be an analog circuit that delivers one voltage level among those connected to its inputs based on the value of logic signals of bus Sn. The selected voltage is then output as Vout. Bus Sn can include selection signals S1, S2, S3, . . . , Sk−1, Sk, . . . , Sn, for example. These logic signals can be generated by a decoder D, which can be a logic circuit that converts coded inputs into coded outputs. Decoder D can receive at its input a signal Dm from a logic circuit L and decode it into the appropriate selection signal S1 through Sn. The inputs to logic circuit L can be trimming signals, which can also be called configuration signals. The trimming signals may be generated from fuses or memory cells/blocks dedicated for this purpose, for example.
To determine the appropriate voltage to select, the various selectable voltage levels can be measured to determine which one is closest to a target value. The target value can be a voltage level that is desired, to serve as a voltage reference signal, for example. The voltage closest to the target value can then be selected and output as Vout by enabling the appropriate configuration signal.
A drawback of this technique and architecture is that PMOS output transistor M might operate with a low saturation margin, especially under low power supply conditions. For example, with reference to FIG. 5, assume that the optimum value to be output by multiplexer MUX1 as Vout V3, because V3 is the closest voltage to the target value. V1, which is the drain voltage of PMOS output transistor M, will be higher than V3. This is because V1 is equal to V3+Vdrop, where Vdrop is equal to the amount that the drain voltage drops from transistor M to node V3. Vdrop can be given by Vdrop=I*Rdrop, where I is the current flowing through transistor M and Rdrop is the sum of the value of the resistors from node V1 to node V3 (i.e., Rdrop=R1+R2). This value could limit the saturation margin of transistor M. As a result, output voltage Vout might become imprecise and sensitive to power supply variations.
The above described problem could compromise the power supply rejection ratio (PSRR). The PSRR is a term used in voltage reference and voltage regulator architectures to describe the amount of noise from a power supply that a particular device can tolerate. Essentially, a given device is capable of rejecting the noise up to its PSRR. The PSRR can be defined as the ratio of the output voltage variation to the change of supply voltage of the device.